1. Field of the Invention
The present invention relates to an isolation for a semiconductor device, and in particular to an improved STI fabrication method for a semiconductor device.
2. Description of the Background Art
The shallow trench isolation (STI) for a known semiconductor device will now be explained with reference to the accompanying drawings.
As shown in FIG. 1A, a first oxide film 2 is formed on a semiconductor substrate 1, and a nitride film 3 is formed on the first oxide film 2. The thickness of the nitride 3 is about 2000 .ANG..
Next, as shown in FIG. 1B, a photoresist pattern 4 is formed on the nitride film 3, and the first oxide film 2 and the nitride film 3 are etched and patterned using the thusly formed photoresist pattern 4 as a mask. At this time, the upper etched portions of the first oxide film 2 and nitride film 3 on the semiconductor substrate 1 are exposed.
As shown in FIG. 1C, the exposed semiconductor substrate 1 is etched using the nitride film pattern 3a as a hard mask for thus forming a trench 5, and a second oxide film 6 is formed on the trench 5 to have a thickness which is the same as the thickness of the first oxide film 2. Thereafter, a third oxide film 7 is formed on the semiconductor substrate 1 including the first oxide film 2, the nitride film pattern 3a and the second oxide film 6 by a high density plasma chemical vapor deposition (HDP CVD) method. After that, the annealing process is processed with respect to the resultant structure. At this time, the trench 5 is filled with the third oxide film 7 (gapfill step).
As shown in FIG. 1D, the third oxide film 7 is etched by a chemical-mechanical polishing method (CMP). At this time, the nitride pattern 3a which serves as an etching stopper is partially etched.
As shown in FIG. 1E, the residual nitride film 3a and the first oxide film 2 are etched and removed, and the conventional STI fabrication method is completed.
However, the STI fabrication method for a known semiconductor device has a problem in that the STI is fabricated using an expensive semiconductor apparatus such as an HDP CVD apparatus and CMP, so that the fabrication cost is increased.
In addition, a predetermined defect may occur on the surface of the semiconductor substrate due to the stress of the thick nitride film when heat-treating the HDP CVD oxide film.
Furthermore, the oxide film of the corner of the trench may be etched beyond the surface height of the semiconductor substrate when etching the HDP CVD oxide film, so that the polysilicon deposited on the corner portion may not be etched after the polysilicon is deposited for thus causing a predetermined isolation therein.